Kurssin kuvaus

Please note that the first lecture (Lecture 1) will be on 1st September, 2025. 

Lecture 1: Introduction- Chip Implementation

Lecture 2: RTL-to-GDSII The Bare Minimum

Lecture 3: Static Timing Analysis (STA)

Lecture 4: Logical Synthesis

Lecture 5: Logical Synthesis- Optimization and DFT

Lecture 6: To Physical Domain-Floor Planning

Lecture 7: Placement

Lecture 8: Clock Tree Synthesis (CTS)

Lecture 9: Routing

Lecture 10: Chip Finishing

Lecture 11: I/O Cells and Packaging

Lecture 12: Low Power Design and Fabrication Process Flow